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INTRODUCTION

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be a part of the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering AI and machine learning workloads in data centers. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU, requiring close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of design methodologies and flows.

As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. You will have the opportunity to address challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

BASIC QUALIFICATIONS

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• 2 years of experience in RTL design.
• Experience with digital design and microarchitecture design.
• Experience in design, optimizing for performance, power, and area.
• Experience with cross-functional engagement with Design Verification and Physical Design teams.

PREFERRED QUALIFICATIONS

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 4 years of RTL design experience.
• Experience with Linting, CDC, RDC, LEC.
• Experience with Scripting languages (i.e. Python or Perl).
• Experience architecting RTL solutions and experience with ASIC Synthesis flows.
• Experience with flow development and methodology improvements, and Integration experience.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with partner teams to support integration efforts and with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies, and support post-silicon validation and debug efforts.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.