Electronics STEM OPT Jobs in California
Electronics F-1 STEM OPT sponsorship jobs in California sit at the center of one of the world's densest hardware and semiconductor ecosystems. Companies like Apple, Qualcomm, and Intel file hundreds of STEM OPT-eligible LCAs annually across Silicon Valley, San Diego, and the Los Angeles basin, covering roles in embedded systems, chip design, RF engineering, and hardware verification.
Find Electronics JobsOverview
Showing 5 of 458+ Electronics STEM OPT Jobs in California










See all 458+ Electronics STEM OPT Jobs in California
Sign up for free to unlock all listings, filter by visa type, and get alerts for new Electronics STEM OPT Jobs in California.
Get Access To All Jobs
INTRODUCTION
This is a hybrid role than can be performed three days per week from our San Jose, CA office.
Meet the Team
Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.
Your Impact
We are looking for a Design-for-Testability (DFT) Engineer to support DFT implementation, validation, and signoff for complex ASIC / SoC designs. The ideal candidate will have hands-on experience with scan insertion, MBIST, ATPG, DFT rule checks, pattern validation, and coverage analysis. This role involves working closely with senior DFT engineers, RTL design, verification, physical design, product engineering, and test teams to help deliver high-quality test coverage and manufacturability for advanced semiconductor designs. Key responsibilities include:
- Support DFT implementation for ASIC / SoC blocks and subsystems
- Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic
- Run DFT rule checks and debug scan, clock, reset, and test-mode issues
- Generate and validate ATPG patterns for stuck-at, transition, and other required fault models
- Analyze test coverage, pattern count, compression results, and ATPG reports
- Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues
- Work with RTL and verification teams to ensure DFT requirements are correctly implemented
- Support block-level and full-chip DFT integration activities
- Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable
- Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting
- Support silicon debug, diagnosis analysis, and yield-learning activities as needed
- Document DFT implementation results, known issues, waivers, and signoff status
MINIMUM QUALIFICATIONS
- Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
- Experience with ASIC DFT implementation or validation
- Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent
- Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls
- Experience with stuck-at and transition fault models
- Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures
- Scripting experience using Tcl, Python, Perl, or shell
PREFERRED QUALIFICATIONS
- Experience with hierarchical DFT methodology and block-level signoff
- Exposure to IJTAG / IEEE 1687, IEEE 1500, boundary scan, or SSN-based flows
- Experience with MBIST insertion, memory test validation, or BISR flows
- Familiarity with gate-level simulation, SDF timing, and pattern validation
- Exposure to silicon bring-up, ATE pattern delivery, failure diagnosis, or yield debug
- Experience working on advanced-node ASICs, networking ASICs, or high-performance SoCs
- Ability to improve automation, regression checks, and DFT reporting dashboards
- Experience with clocking, reset, timing constraints, and multi-clock-domain scan implementation
- Scripting experience using Tcl, Python, Perl, or shell
- Experience troubleshooting problems related to ASIC DFT and working with cross-functional teams.
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.
Message to applicants applying to work in the U.S. and/or Canada:
The starting salary range posted for this position is $155,000.00 to $222,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:
- 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
- Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
- Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
- 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:
- .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
- 1.5% of incentive target for each 1% of attainment between 50% and 75%;
- 1% of incentive target for each 1% of attainment between 75% and 100%; and
- Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
The applicable full salary ranges for this position, by specific state, are listed below:
New York City Metro Area:
$155,000.00 - $256,000.00
Non-Metro New York state & Washington state:
$138,100.00 - $227,900.00
- For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.
STEM OPT Electronics Job Roles in California
See all 458+ Electronics STEM OPT Jobs in California
Sign up for free to filter by visa type, set job alerts, and find employers with verified sponsorship history.
Search Electronics Jobs in CaliforniaElectronics STEM OPT Sponsorship Jobs in California: Frequently Asked Questions
Which electronics companies in California sponsor F-1 STEM OPT visas?
California's largest electronics and semiconductor employers have consistent STEM OPT sponsorship histories documented in DOL Labor Condition Application filings. Companies such as Apple, Qualcomm, Intel, Broadcom, NVIDIA, and Applied Materials appear frequently in those records across hardware engineering, chip architecture, and firmware roles. Defense electronics contractors like Raytheon and L3Harris also file in California, though those roles may carry additional security clearance requirements that can complicate sponsorship.
Which California cities have the most electronics F-1 STEM OPT sponsorship jobs?
Silicon Valley cities, including San Jose, Santa Clara, and Sunnyvale, account for the highest concentration of electronics STEM OPT-eligible roles given the density of semiconductor and hardware firms headquartered there. San Diego is a secondary hub with strong activity in wireless and RF engineering, driven by Qualcomm and its supplier network. Los Angeles and the South Bay host aerospace electronics and defense hardware employers, while Sacramento has a smaller but active power electronics and utility-tech cluster.
What types of electronics roles typically qualify for F-1 STEM OPT sponsorship?
Roles that qualify for STEM OPT are tied to degrees in USCIS-designated STEM fields, not to the job title alone. In electronics, that typically covers positions in hardware engineering, semiconductor design, embedded systems development, signal processing, RF and antenna engineering, PCB design, and test engineering when filled by graduates holding degrees in electrical engineering, computer engineering, or related STEM disciplines. O*NET classifications can help confirm whether a specific role falls within a STEM-designated occupation category.
How do I find electronics F-1 STEM OPT sponsorship jobs in California?
Migrate Mate surfaces electronics roles in California filtered by employers with verified STEM OPT and H-1B visa LCA filing history, so you can focus on companies that have sponsored international candidates in hardware and semiconductor roles before. Searching by occupation and filtering to California lets you identify active STEM OPT-eligible postings in cities like San Jose, San Diego, and Santa Clara without sifting through employers with no sponsorship track record.
Are there California-specific considerations for F-1 STEM OPT sponsorship in electronics?
California's strong labor protections and prevailing wage requirements mean employers filing LCAs for electronics roles must meet DOL wage standards, which you can verify using the OFLC Wage Search tool by occupation and county. California also has a large proportion of electronics employers enrolled in E-Verify, a federal requirement for STEM OPT employers. Some defense electronics roles in the state require U.S. citizenship or security clearances, which would make STEM OPT sponsorship impossible regardless of employer willingness.