Senior Physical Design Engineer Jobs in California
Senior Physical Design Engineer jobs in California represent one of the most active markets in the country, concentrated in the semiconductor, consumer electronics, and fabless chip design sectors that define California's technology economy. The heaviest hiring is in San Jose, San Diego, and Santa Clara, where companies like Qualcomm, Apple, and NVIDIA maintain large physical design teams at every level from associate through principal engineer. The most consistently in-demand specialties are place-and-route, static timing analysis, and physical verification for advanced process nodes. Find a role that fits below and apply directly.
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Showing 5 of 14+ Senior Physical Design Engineer jobs
Job Details
Job Description:
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must possess a bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 6+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 4+ yrs. of experience in:
VLSI circuit design and synthesis.
Static timing analysis.
* Low power design.
Preferred Qualifications
2+ years of experience in:
x86 CPU architecture.
Tcl/Perl/Python programming.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
Business Group
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00 - 232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
- Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION:
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Details
Job Description:
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high-speed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must possess a bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 6+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 4+ yrs. of experience in:
VLSI circuit design and synthesis.
Static timing analysis.
* Low power design.
Preferred Qualifications
2+ years of experience in:
x86 CPU architecture.
Tcl/Perl/Python programming.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
Business Group
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00 - 232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
- Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION:
Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
See All 14 Senior Physical Design Engineer Jobs in California
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Find JobsSenior Physical Design Engineer Jobs by City in California
Where California roles are concentrated, by current openings.
Senior Physical Design Engineer Job Market in California
A snapshot from current California openings, updated as new roles post.
Who's Hiring
- Intel4
- Astera Labs3
- Cisco2
- Credo Semiconductor2
- Eliyan1
Top Industries Hiring
- Electronics & Hardware12
- Technology & Software5
- Consulting & Professional Services1
What California Employers Look For
The qualifications that appear most often in senior physical design engineer jobs across California.
- Bachelor's or master's degree in electrical engineering or computer engineering required
- Five or more years of hands-on place-and-route experience at advanced process nodes
- Proficiency with industry-standard EDA tools such as Cadence Innovus or Synopsys ICC2
- Demonstrated experience with static timing analysis, power integrity, and signal integrity closure
- Strong understanding of DRC, LVS, and physical verification flows for leading-edge foundries
- Experience taping out complex SoC or custom digital designs at 7nm or below preferred
Senior Physical Design Engineer Jobs in California: Frequently Asked Questions
How do you become a senior physical design engineer in California?
The most direct path is a bachelor's or master's degree in electrical engineering or computer engineering, followed by several years of progressively complex physical design work. California does not require a state-issued license for this role. Hiring teams at California semiconductor companies typically look for candidates who have contributed to a full tapeout cycle, can demonstrate closure experience at advanced nodes, and are familiar with the EDA tool flows those specific teams use.
How much do senior physical design engineers make in California?
Senior physical design engineers in California earn a median of about $185,180 a year, based on May 2025 Bureau of Labor Statistics wage data, ranging from around $126,590 for the lowest 10% to over $281,210 for the top 10%. Pay rises with experience, specialty, and employer.
Which companies hire senior physical design engineers in California?
Employers hiring senior physical design engineers in California right now include Intel, Astera Labs, and Cisco, based on current listings on Migrate Mate as of June 2026. California's concentration of fabless semiconductor companies and large consumer electronics hardware teams means hiring is sustained across the state's major tech corridors year-round.
Which California cities have the most senior physical design engineer jobs?
The cities with the most senior physical design engineer openings in California are San Jose, Folsom, and Santa Clara. The distribution follows California's semiconductor and consumer electronics footprint, with the Silicon Valley corridor anchoring the largest share of roles because of the dense cluster of fabless chip companies and major hardware-focused technology headquarters concentrated there.
Are there remote senior physical design engineer jobs in California?
Yes, but they're relatively limited. Physical design work involves close collaboration with timing, verification, and foundry teams, and many California employers expect on-site or hybrid presence for tapeout-critical phases. About 36% of senior physical design engineer openings tied to California are remote or hybrid as of June 2026. The tasks most suited to remote work are timing analysis reviews, scripting, and flow development rather than active closure work.
How can I get hired as a senior physical design engineer in California with little or no experience?
The most realistic entry point is a master's degree program at a California university with a strong VLSI curriculum, which many California semiconductor companies actively recruit from through on-campus programs. Pursuing entry-level physical design or design verification roles at mid-size fabless companies in San Jose or San Diego is a concrete first step, as those teams often grow associates into full place-and-route contributors. Building a portfolio that includes a completed tapeout project, even from an academic or open-source context, gives candidates a clear edge over those without demonstrated tool experience.
Where can I find and apply to senior physical design engineer jobs in California?
You can find and apply to senior physical design engineer jobs in California on Migrate Mate, which lists current California openings. Find the roles that fit your experience and apply directly.
See All 14 Senior Physical Design Engineer Jobs in California
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