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Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Senior / Distinguished Member of Technical Staff — Silicon Photonics Engineer (Interface Pathfinding)

About the Role

At Micron, we transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next era of AI, ML, and advanced computing.

Micron’s Interface Pathfinding team operates at the leading edge of that mission — driving performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. A critical new dimension of that work is optical interconnect — and we are hiring a photonics engineer to establish and lead that technical discipline within the team.

As a Silicon Photonics Engineer, you will be the team’s resident photonics subject-matter expert — guiding technology selection, independently evaluating partner PIC designs, co-specifying test-chip architectures with the electrical I/O team, and building the technical foundation for photonic interconnect at Micron.

Why This Role

• You will define a new technical discipline at Micron — this is not a backfill; you are building the photonics function from the ground up.
• You will work alongside genuinely exceptional analog and digital designers in an environment where engineers work as genuine collaborators, not in silos.
• The team is intentionally small and senior — decisions get made quickly, bureaucracy is minimal, and your judgment will be trusted.
• You are joining an active program with real momentum — your technical direction will directly shape its trajectory and scope going forward.

What You’ll Own

• Photonic Technology Direction: Serve as Micron’s internal SME on silicon photonics — evaluate competing optical interconnect approaches and provide grounded, data-driven technology recommendations to program leadership.
• Partner PIC Design Evaluation: Independently verify and critically assess partner PIC designs — run simulations, validate performance claims, perform sensitivity and tolerance analyses, and identify design risks that partners may understate.
• Test-Chip Co-Specification: Collaborate with the electrical I/O team to define test-chip features, test structures, and measurement interfaces required to evaluate photonic link performance.
• Link Architecture & Budgeting: Develop optical link budgets, define modulation format and wavelength strategy, and establish loss, power, and BER targets for photonic interconnect proof-of-concepts.
• Behavioral Modeling: Build photonic behavioral models (Verilog-A, real-number modeling, or equivalent) that integrate into the team’s mixed-signal co-simulation environment — enabling system-level analysis across the electrical-optical boundary.
• Optical Characterization: Define optical test and measurement requirements for post-silicon bring-up.
• Design Documentation: Author technology assessments, link budget analyses, partner design reviews, and test-chip specifications that serve as the authoritative reference for photonic interconnect decisions.

What You’ll Work On

The Interface Pathfinding team designs and validates novel PHY solutions for high-speed interconnect. The photonics scope extends that mission into the optical domain, with responsibility spanning device-level evaluation through link-level architecture.

Key photonics domains include:

• Optical Interconnect Architecture — waveguide routing, fiber-to-chip coupling, grating coupler and edge coupler evaluation, and optical path integration with advanced packaging
• Silicon Photonic Devices — modulators, filters, photodetectors, and wavelength-division multiplexing structures as designed by foundry partners
• Electro-Optical Interface — the critical boundary between photonic components and electrical PHY circuits (driver modulator, photodetector TIA), including co-design constraints and impedance/bandwidth matching
• Test-Chip Definition — working with analog and digital leads to ensure test-chip architectures include the structures and interfaces needed to characterize photonic link performance on real hardware

What You Bring

Required

• MS or PhD in Electrical Engineering, Physics, Photonics, or related field
• 10+ years of experience in silicon photonics, photonic integrated circuit design, or optical interconnect development
• At least one silicon photonics fabrication cycle (PIC tape-out or MPW shuttle run) in a primary design or integration role
• Proficiency with photonic simulation tools (Lumerical, Synopsys OptoDesigner, Photon Design, or equivalent)
• Solid understanding of silicon photonics process fundamentals — waveguide design rules, modulator and photodetector device physics, and PDK-based design flow
• Experience developing optical link budgets and evaluating photonic link performance (insertion loss, coupling efficiency, modulation depth, BER)
• Strong written communication skills — this role produces technology assessments and specifications, not just simulations
• It is expected that the candidate will be proficient in leveraging AI for productivity

Preferred

• Familiarity with foundry PDKs for silicon photonics (AIM Photonics, GlobalFoundries, Tower, TSMC COUPE, or equivalent)
• Experience with co-packaged optics or optical I/O for compute or memory applications
• Post-silicon optical characterization experience — correlating simulated photonic performance to measured results on real hardware
• Familiarity with high-speed electrical PHY architectures (SerDes, DDR, or die-to-die interfaces) and how they mate with photonic front-ends

A Note to All Candidates

These roles are part of a deliberate effort to build a long-term, high-caliber team around a compelling PHY technology program. We are looking for engineers who want to own something, build something, and grow with a program. If that description resonates, we’d like to hear from you.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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