Electronics E-3 Sponsorship Jobs in Oregon
Electronics E-3 visa sponsorship jobs in Oregon are concentrated in the Portland metro area, home to major employers like Intel, Tektronix, and Daimler Trucks North America's electronics division. The state's semiconductor and hardware engineering sectors regularly hire for roles that meet E-3 specialty occupation requirements, making Oregon one of the stronger markets for Australian electronics professionals.
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Job Description:
About the Role
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.
In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
What You’ll Do
Key responsibilities will include but not limited to:
- Developing layout design methodology for testchip development in next generation process nodes
- Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
- Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
- Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
- Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Behavioral traits that we are looking for:
- Exhibiting strong interest in Layout design in advanced technology nodes.
- Strong verbal and written communication skills
- Ability to work well both autonomously and in an intensive, cooperative team environment
- Coordinate between different stakeholders for testchip to arrive at execution commit for testchip
- Motivation to continuously learn and drive to push improved layout productivity and efficiency
Why Join Us
- Work on cutting-edge semiconductor technologies that shape the future of computing
- Collaborate with industry-leading experts across design and manufacturing
- Opportunities for career growth and technical leadership
- Contribute to innovations that impact global technology at scale
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life
See Intel Benefits for more details.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
- Experience with physical/layout design in advance technology nodes
- In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
- Design rules and layout constraints in advanced semiconductor processes
- Experience with floorplanning, hierarchical design integration, and layout verification/debug
Preferred Qualifications and Experience:
- Experience in Definition of Testchip/Product design from Concept to Execution Commit
- Experience in working with Foundry teams on negotiating features to exercise in design
- Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
- Previous related work experience in a semiconductor foundry preferred
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Texas, Austin
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers - from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Job Details:
Job Description:
About the Role
Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.
In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.
What You’ll Do
Key responsibilities will include but not limited to:
- Developing layout design methodology for testchip development in next generation process nodes
- Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.
- Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration
- Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
- Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools
- Working with tool/flow owners and vendors for ongoing tool/methodology improvement
Behavioral traits that we are looking for:
- Exhibiting strong interest in Layout design in advanced technology nodes.
- Strong verbal and written communication skills
- Ability to work well both autonomously and in an intensive, cooperative team environment
- Coordinate between different stakeholders for testchip to arrive at execution commit for testchip
- Motivation to continuously learn and drive to push improved layout productivity and efficiency
Why Join Us
- Work on cutting-edge semiconductor technologies that shape the future of computing
- Collaborate with industry-leading experts across design and manufacturing
- Opportunities for career growth and technical leadership
- Contribute to innovations that impact global technology at scale
- Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life
See Intel Benefits for more details.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
- Experience with physical/layout design in advance technology nodes
- In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler
- Design rules and layout constraints in advanced semiconductor processes
- Experience with floorplanning, hierarchical design integration, and layout verification/debug
Preferred Qualifications and Experience:
- Experience in Definition of Testchip/Product design from Concept to Execution Commit
- Experience in working with Foundry teams on negotiating features to exercise in design
- Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in
- Previous related work experience in a semiconductor foundry preferred
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara, US, Texas, Austin
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers - from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
E-3 Electronics Job Roles in Oregon
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Search Electronics Jobs in OregonElectronics E-3 Sponsorship Jobs in Oregon: Frequently Asked Questions
Which electronics companies sponsor E-3 visas in Oregon?
Intel is Oregon's largest electronics employer, operating major chip fabrication and design facilities in Hillsboro. Tektronix, headquartered in Beaverton, sponsors for test and measurement engineering roles. Epson Portland, Lattice Semiconductor, and Planar Systems have also filed Labor Condition Applications for electronics positions. Sponsorship availability changes with hiring cycles, so confirming directly with each employer's recruiting team is essential.
Which cities in Oregon have the most electronics E-3 sponsorship jobs?
The Portland metro area, particularly Hillsboro and Beaverton in Washington County, concentrates the majority of Oregon's electronics sponsorship opportunities. This corridor is anchored by Intel's large campus and a cluster of semiconductor and hardware firms. Portland itself hosts additional electronics and embedded systems employers. Outside the metro, Eugene has a smaller but active electronics engineering presence through companies serving the defense and communications sectors.
What types of electronics roles typically qualify for E-3 sponsorship?
Roles that consistently qualify include hardware design engineer, embedded systems engineer, VLSI design engineer, PCB layout engineer, semiconductor process engineer, and RF engineer. These positions require a bachelor's degree or higher in electrical engineering, electronics engineering, or a closely related field. The degree must directly correspond to the duties of the role. General technician or assembly positions typically do not meet the specialty occupation standard required for E-3 visa approval.
How do I find electronics E-3 sponsorship jobs in Oregon?
Migrate Mate is built specifically for this search. You can filter by E-3 visa type and the electronics industry to see Oregon-based roles from employers with a documented history of visa sponsorship. This saves significant time compared to sifting through general job listings where sponsorship availability is rarely disclosed upfront. Migrate Mate surfaces positions where employers have already filed Labor Condition Applications, which is a strong indicator of E-3 sponsorship willingness.
Are there any Oregon-specific considerations for electronics E-3 sponsorship?
Oregon's semiconductor sector operates on project-driven hiring cycles tied closely to Intel's expansion phases and broader chip industry demand. E-3 applicants in hardware and semiconductor roles may encounter employers familiar with the visa process given the state's international workforce. Australian three-year bachelor's degrees in electrical or electronics engineering are generally accepted as equivalent to U.S. four-year degrees, but individual employers and their immigration counsel make the final determination on degree equivalency.
What is the prevailing wage for E-3 electronics jobs in Oregon?
U.S. employers sponsoring a visa must pay at least the prevailing wage, which is what workers in the same role, area, and experience level typically earn. The Department of Labor sets this rate to make sure companies aren't hiring foreign workers simply because they'd accept lower pay than a U.S. worker. It varies by job title, location, and experience. You can look up current prevailing wage rates for any occupation and location using the OFLC Wage Search page.